general description deepcover? embedded security solutions cloak sensitive data under multiple layers of advanced physical security to provide the most secure key storage possible. the deepcover secure microcontroller (MAXQ1851) is a low- power, 32-bit risc device designed for electronic commerce, banking, and data security systems. it combines high-perfor - mance, single-cycle processing, sophisticated tamper-detec - tion technology, and advanced cryptographic hardware to pro - vide industry-leading data security and secret key protection. physical security mechanisms include environmental sen - sors that detect out of range voltage or temperature con - ditions, responding with rapid zeroization of critical data. four self-destruct inputs are provided for additional tam - per response. an internal shield over the silicon provides protection from microprobe attacks. a high-speed internal ring oscillator is provided to thwart attacks that rely on controlling the clock rate of the chip. to protect data, the MAXQ1851 integrates several high-speed encryption engines. algorithms supported in hardware include aes (128-, 192-, and 256-bit), des, triple des (2-key and 3-key), ecdsa (160-, 192-, and 256-bit keys), dsa, rsa (up to 2048 bits), sha-1, sha-224, and sha-256. the devices advanced security features are designed to meet the stringent requirements of regulations such as itsec e3 high, fips 140-2 level 3, and the common criteria certifications. the MAXQ1851 includes 256kb of flash memory, 8kb of sram, 4kb of aes encryptable battery-backed sram, and 256-bit secure, battery-backed, flip-flop-based key storage. several communication protocols are supported with hardware engines, including iso 7816 for smart card applications, usb (slave interface with four end-point buf - fers), an rs-232 universal synchronous/asynchronous receiver-transmitter (usart), an spi interface (master or slave mode support), and up to 16 general-purpose i/o pins. other peripherals supported on the MAXQ1851 include a true hardware random-number generator (rng), a real-time clock (rtc), a programmable watchdog timer, and flexible 16-bit timers that support capture, compare, and pulse-width modulation (pwm) operations. applications electronic commerce emv ? banking secure access control secure data storage pay-per-play certifcate authentication electronic signature generation features high-performance, low-power, 32-bit maxq30 risc core single 3.3v supply enables low power/flexible interfacing dc to 16mhz code execution across entire operating range on-chip 2x/4x clock multiplier 33 instructions 16-bit instruction word, 32-bit internal data bus 16 x 32-bit accumulators virtually unlimited software stack optimized for c-compiler (high-speed/density code) security features ? 65mhz cryptography engine execution to reduce processing time ? unique id ? tamper detection with fast wipe key/data destruction ? 4 self-destruct inputs ? hardware aes and des engines ? public key cryptographic accelerator for dsa, ecdsa, and rsa ? supports sha-1, sha-224, and sha-256 ? true hardware rng and prng ? unalterable, battery-backed rtc ? hardware crc-32/16 memory ? 256kb flash, composed of 2048-byte pages (20k erase/write cycles per sector) ? 8kb sram, 4kb battery-backed sram ? 256-bit, battery-backed, flip-flop-based secure key storage ? dedicated cryptographic memory space i/o and peripherals ? up to 16 general-purpose i/o pins ? 5v tolerant i/o ? power-fail warning ? power-on reset/brownout reset ? jtag i/f for system programming and accessing on-chip debugger ? usb i/f with four end-point buffers ? iso 7816 smart card uart with fifo ? 4 16-bit timer/counters, two with pwm function ? spi and usart communication ports ? programmable watchdog timer low-power consumption ? 550na typ current draw in battery-backed mode, preserving 4kb aes encryptable nv sram and 256-bit flip-flop-based secure master key storage, with security sensors active (1.5a with rtc and active die shield enabled) 19-6618; rev 0; 5/13 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAXQ1851.related . deepcover is a registered trademark of maxim integrated products, inc. emv is a registered trademark of emvco llc. MAXQ1851 deepcover secure microcontroller with fast wipe technology and cryptography abridged data sheet
maxim integrated 11 block diagram detailed description the MAXQ1851 is designed for electronic commerce, banking, and data security systems that require secure access control, secure data storage, digital signature, or certificate authentication. for example, it can be used for pin pads and to act as a coprocessor for higher end pos terminals. the controller combines low power operation with high-performance cryptographic accelerators, advanced security features, and advanced semiconductor process technologies to meet the most stringent needs of security applications. sensitive data such as keys are shielded within and never need to leave the MAXQ1851, thwarting pcb level attacks. on-chip tamper sensors and an internal active die shield deter physical attacks against the device. custom-designed cryptographic hardware and unique countermeasures protect against logical and statistical attacks, such as differential or simple power analysis. the MAXQ1851 provides self-destruct inputs (sdi1?sdi4) as well as a multitude of environmental monitors including temperature, battery voltage, and v dd voltage. the MAXQ1851 offers a rich set of peripherals including serial i/o, spi, usb, and iso 7816 smart card interfaces for efficient communication. each MAXQ1851 has a universally unique identification number for device management and to prevent cloning. the MAXQ1851 contains the hardware-accelerated cryptography units required for system certification under itsec e3 high, fips 140-2 level 3, common criteria, and the usps pcibi-c standard. the MAXQ1851 is designed to meet the security requirements of the visa pci (payment card industry) specification as part of an overall system solution. the cryptographic accelerator supports both symmetric cryptography (aes, des, 3des, both two-key and three- key) and asymmetric cryptography (rsa, dsa, ecc). the MAXQ1851 can internally generate, store, and check digital signatures (dsa, ecdsa, rsa), secure hash algorithms (sha), and cryptographic keys; a secure, fips 186-2-compliant hardware rng and an rtc are built into the device. +denotes a lead(pb)-free/rohs-compliant device. *ep = exposed pad. ordering information note to readers: this document is an abridged version of the full data sheet. additional device information is available only in the full version of the data sheet. to request the full data sheet, go to www.maximintegrated.com/MAXQ1851 and click on request full data sheet . part temp range pin-package MAXQ1851-bns+ -40c to +85c 40 tqfn-ep* core osc ecdsa rsa 8kb sram 4kb nv sram gpio maxq30 core iso 7816 spi usb usart dsa des aes rng timers jtag/ debug 256kb flash utility rom crypto osc rtc pll 32khz 12mhz MAXQ1851 note: the block diagram shows a typical system clock used to support usb operation at 12mhz. multiple external crystal/clock option s are available. MAXQ1851 deepcover secure microcontroller with fast wipe technology and cryptography www.maximintegrated.com abridged data sheet
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